The design dimensions of ultra-high integration circuits (ULSI) formed on a Si semiconductor substrate are being made ever smaller due to the need for reducing costs, improving performance, and minimizing power consumption. Functionality is improved by reducing the dimensions and increasing the number of integrated elements, and costs are lowered by reducing the chip size. Improving the degree of integration further allows a plurality of circuit blocks having different functions to be combined, and reducing the number of components enables the cost of devices in which ULSI chips are incorporated to be lowered. So combining circuit blocks having varied functions in this manner not only results in lower costs, but allows communication speeds to be improved and other benefits to be realized. Further performance-related enhancements can also be achieved by incorporating circuit blocks having diverse functionality. Reducing the design dimensions also allows the operating voltage to be lowered, which enables the power consumed by the circuit bocks sharing the same function to be minimized.
However, new problems have been encountered as the size of the active elements becomes progressively smaller. Such problems are described below in relation to categories such as power supply noise, RF/analog circuits, and memory.
Problems associated with power supply noise shall be described first. The voltage decreases as the size of the elements is reduced, but the number of integrated elements increases sharply; therefore, the amount of current consumed increases sharply as well. Furthermore, as the elements become smaller, the operating frequency increases and the switching time decreases. Specifically, the amount of current used during switching increases, and the switching time decreases; therefore, the change in current over time (di/dt) sharply increases. L·di/dt, which is obtained by multiplying the circuit inductance L by the change in current over time, is the inductive voltage variation, and is known as “simultaneous switching noise.” Simultaneous switching noise causes the power supply potential to fluctuate, and occasionally reverses the logic state. Not only does the power supply voltage decrease as the dimensions are made smaller, as described above, but noise-derived fluctuations in voltage increase. The noise margin accordingly decreases at an accelerated pace. The inductive noise can be reduced by lowering the impedance of the circuit, and variation in the power supply can be suppressed by introducing a capacitor to the circuit. Such a capacitance is referred to as a decoupling capacitance. In conventional ULSIs, a MOS capacitance obtained when the transistors are formed is used as the decoupling capacitance. However, MOS capacitance insulating films become thinner as design dimensions continue to decrease, and a problem arises in regard to the sharp increase of leakage current in the insulating films. The noise margin also drops precipitously; therefore, the absolute capacitance becomes inadequate, and a tendency is shown whereby the surface area of the chip is increased by a decoupling capacitance, which is introduced in order to stabilize the power supply potential. In order to circumvent such problems, it is necessary to provide the wiring layer with a decoupling capacitance which is higher than the MOS capacitance and in which an insulating film having a dielectric constant is used. Incorporating capacitance in the wiring layer enables the capacitance to be placed on top of the transistor as seen in a plan view, and the mounting surface area can therefore be made greater than that of the MOS capacitance. Increasing the dielectric constant enables greater capacitance to be obtained in the same area, and thereby allows a large capacitance to be established within a limited area. By way of example, the films shown in patent documents 1 through 4 may be used as high-dielectric insulating films.
Improvements in operating speed due to the miniaturization of MOS active elements make it easier to design radio-frequency (RF) signal processing circuits as MOS devices. If RF devices can be built using MOS devices, then combining them with a digital baseband circuit will result in functional enhancements, cost reductions, and other benefits. Similar advantages can be obtained by combining analog circuits with digital circuits. Resistor elements, capacitor elements, inductors, and other passive elements can be efficiently used in RF or analog devices. Accordingly, it is of profound importance to integrate passive elements along with the active elements used in MOS logic circuits. MOS logic circuits become increasingly miniaturized with each generation, but the characteristics of passive elements are determined solely on their physical properties, for which reason such elements do not undergo further miniaturization with each generation. Accordingly, the relative surface area of passive elements increases in ULSI chips, and is a factor in preventing the chip cost from decreasing. With capacitor elements, the fact that a parasitic capacitance is formed between the electrodes and the silicon substrate is also a problem associated with operating characteristics. As ULSIs are made smaller, their structure shrinks in three dimensions, causing the distance between the wiring layer and the substrate to decrease. At the same time, the capacitor element electrode area increases in relation to the surrounding circuit, and the parasitic capacitance formed with the substrate is thereby increased. The increase in the relative size of the area also makes the parasitic resistance of the electrodes harder to disregard. In order to resolve the aforedescribed problems, high-dielectric capacitor elements are preferably positioned further apart from the substrate. More specifically, the capacitor elements need to be provided to the uppermost wiring layer.
The miniaturization of the manufacturing process also exacerbates problems with memory device. SRAM is used as CMOS memory. SRAM holds the memory state by latching logic signals in a CMOS circuit in a complementary fashion. In recent years, with the progress in miniaturization, the gate capacitance has decreased, and problems have been encountered in that the logic is inverted by charges produced by alpha rays or cosmic rays. Such errors are referred to as soft errors. Soft errors in a SRAM signify damage to the memory state, which is a serious problem. In order to solve such problems, there have been attempts to add capacitor elements to memory nodes for the purpose of obtaining an equivalent increase in gate capacitance.
Many problems are solved in this manner by adding capacitor elements in the wiring layer. However, new problems are created by the addition of capacitor elements in the wiring layer. One of them concerns the heat resistance of the insulation film in a state-of-the-art wiring structure wherein the wiring material primarily composed copper is formed in the interlayer insulation film having a low dielectric constant. This imposes an upper limit on the processing temperatures, which range from 350 to 400° C. Accordingly, the temperature at which capacitor elements are formed must be set to 350° C. as the upper limit. Since copper is easily diffused in an insulation film, a barrier film for reducing the diffusion of copper must be disposed between the interlayer insulation film, the capacitor insulation film, and the cooper wiring. In view of the above, careful consideration must be given to the structure and manufacturing process of the capacitor elements to be formed in the copper wiring.
Described below are disclosed examples of capacitor element structures and manufacturing methods devised for the purpose of forming a capacitance in a wiring layer.
(Prior Art 1)
Patent Document 5 discloses a structure in which a capacitor element is added to a cell in order to improve resistance to soft errors in an SRAM. The structure in this document is one in which a capacitor element having a stacked structure is formed from upper and lower electrodes that cover the upper portion of the memory cell, and from a capacitor insulation film disposed between the electrodes. Also, in the document, polysilicon is used as the electrode material, and silicon nitride film is used as the capacitor insulation film.
(Prior Art 2)
Patent Document 6 discloses a structure in which a material other than nitrogen carbide or silicon carbide can be used for the capacitor dielectric film. The technique in this document relates to a capacitor structure formed on a multilayered wiring structure having copper wiring. With a structure having conventional copper wiring, a nitrogen carbide film or silicon carbide film is necessarily formed as an antioxidation insulation layer on the copper wiring. For this reason, these films must be used as capacitor insulation films in order to form a capacitor on the copper wiring. The technique used in this document is used for avoiding such restrictions. With the technique described in the document, a metal film rather than an insulation film is used as the antioxidation film. A barrier metal is disposed between the exposed surface of the copper wiring and the metal film. This metal film is formed so as to remain on the copper wiring, and the capacitor insulation film is formed on the metal film. In this case, only the interlayer insulation film is exposed in the portion that excludes the metal film exposed as the lower electrode on the copper wiring, and the lower electrode has greater oxidation resistance than the copper wiring. The metal oxide dielectric film can thereby be used as the capacitor insulation film.
(Prior Art 3)
Patent Document 7 discloses a method whereby a capacitor element obtained using a Ta2O5 dielectric film is formed on copper wiring. In this case, a Ta film is disposed between the Cu film and the Ta2O5 film in order to prevent Cu diffusion. The Ta film is slightly oxidized when the Ta2O5 film is formed, but there is also an effect whereby oxidation of the underlying copper wiring is reduced.
(Prior Art 4)
Patent Document 8 discloses a structure for a semiconductor device in which the copper wiring structure is connected to the lower surface of the lower electrode, and an electric charge is supplied to the lower electrode via the copper wiring. This structure makes it possible to prevent the diffusion of copper into the interlayer insulation film and other oxide films, and to allow the wiring to function in a reliable manner. This semiconductor device has an MIM capacitance provided with a lower electrode connected to the upper surface of one or a plurality of wires, and an upper electrode that is connected via capacitive coupling to the lower electrode. The lower electrode is composed of a material that prevents the diffusion of the wiring material. A wiring structure is also enclosed. In this structure, an insulation film, which is ordinarily formed after the copper wiring has been formed and which prevents copper from oxidizing and diffusing, is opened only in the capacitance formation portions, and the lower electrode and the copper wiring of the lower layers are connected via these openings.    [Patent Document 1] Japanese Laid-Open Patent Application No. 7-3431    [Patent Document 2] Japanese Laid-Open Patent Application No. 7-111107    [Patent Document 3] Japanese Laid-Open Patent Application No. 9-67193    [Patent Document 4] Japanese Laid-Open Patent Application No. 10-173140    [Patent Document 5] Japanese Laid-Open Patent Application No. 2004-6850[Patent Document 6] Japanese Laid-Open Patent Application No. 2004-14761    [Patent Document 7] Japanese Laid-Open Patent Application No. 2003-264236    [Patent Document 8] Japanese Laid-Open Patent Application No. 2003-264235